1. Field
The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device and related devices.
2. Description of the Related Technology
In some complimentary metal-oxide-silicon (CMOS) technologies, an n-channel metal-oxide-silicon (NMOS) device and a p-channel metal-oxide-silicon (PMOS) device that are under different types of strains are used. For example, a combination of tensile-strained/unstrained and compressively strained channel structures may be formed on a single substrate for NMOS and PMOS transistor devices, respectively. The different types of strains are employed, e.g., to improve carrier mobilities of the NMOS and PMOS devices.
A prior art solution is to provide different channel materials for the tensile-strained and compressively strained channel structures (channel layers).
At advanced technological nodes, there exists definitely a need for channel materials having a higher mobility than the conventional strained and unstrained Si channel reference device, aiming at further boosting the device performance. However, using different channel materials, e.g., Ge-based materials for PMOS and III-V-based materials for NMOS, can be technologically difficult and expensive.
In many aspects, e.g., the relative compatibility with silicon-based processes, using a germanium-based channel material is advantageous.
In Yang, Appl. Phys. Lett. 91, 102103 (2007), (111) Ge surface properties have been reported as having improved electron transport at any channel strain conditions as compared to the sidewall (110) or top (100) Ge surface.
However, there exists a need for methods which allow manufacturing both tensile-strained and compressively strained channel structures using the same channel material on a substrate, such as for instance a germanium-based channel material.
A big challenge here is the production of Ge n-channel devices. Indeed, relaxed Ge fins having very low defect density are needed for high intrinsic electron mobility. In conventional planar Ge nFETs (e.g. with (100)-Ge as a dominant carrier transport plane), a poor mobility using standard gate stacks has been extensively reported. As a most recent example, C. H. Lee al. at VLSI 2014, technology symposium, page 144 from proceeding (technology symposium)) reported a value of 300 cm2/V·s for the mobility while on (111)-oriented surface (planar) the mobility can exceed 400 cm2/V·s.